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HDL Based Design (2016 Autumn)

Organisation: UTU / Dept. of Information Technology

Credit Points: 5

Responsible Person: Pasi Liljeberg

Course code: DTEK8067

Learning outcomes:
To learn how to design digital systems with hardware description languages (HDLs), especially VHDL to get hands on experience on design flow for modern electronic systems. Is able to used modern CAD tools for simulation and synthesis for performance and trade-off studies towards implementation. Understands synthesis and simulation constraints including timing closures as well as power and area constraints

VHDL syntax and coding styles. Modeling combinational and sequential components as well as data paths and control systems. Design flow. Simulation as a verification method and the creation of testbenches for simulations. Synthesizable VHDL, synthesis process and constraining for synthesis. The usage of modern CAD tools for simulation and synthesis. Introduction to Verilog.



  1. Wed 21.9.–26.10. weekly at 8:30–10, 110C, Agora
  2. Thu 22.9.–27.10. weekly at 10–12, 110C, Agora


  1. Fri 30.9.–16.12. weekly at 8–10, 453, Agora
  2. Fri 30.9.–16.12. weekly at 10–12, 453, Agora
  3. Fri 30.9.–16.12. weekly at 12–14, 453, Agora
  4. Fri 30.9.–16.12. weekly at 14–16, 453, Agora