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HDL Based Design ( 2012 Autumn )

• Organisation: UTU / Dept. of Information Technology
• Credit Points: 5
• Course starts at: 2012-09-04
• Lecturer Person: Masoud Daneshtalab
• Lecturer Person Contact: masdan@utu.fi

• Luennot:
  Tue 10-12 B2038
  Thu 10-12 B2038

• Course Description:

  To learn how to design digital systems with hardware description languages (HDLs), especially VHDL to get hands on experience on design flow for modern electronic systems. Is able to used modern CAD tools for simulation and synthesis for performance and trade-off studies towards implementation. Understands synthesis and simulation constraints including timing closures as well as power and area constraints.
  This course covers:

  VHDL syntax and coding styles.

  Modeling combinational and sequential components.

  Data paths and control systems.

  Design flow.

  Introduction to Verilog.

  Simulation as a verification method and the creation of test-benches for simulations.

  Synthesizable VHDL, synthesis process and constraining for synthesis.

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